The use of digital data transmission systems to send digitally encoded data, which may be for example, voice data, is well known in the art. Such systems require that the receiving end recover the correct phase of the bit rate clock used at the sending end for timing the data transmission. System of this type generally employ some sort of phase-locked loop (PLL) circuitry in order to perform real-time phase correction. In data transmission systems which operate in noisy environments, a narrow operating bandwidth, or narrow-loop mode, is generally preferred for the PLL. However, in order to ensure a fast initial lock of the local clock to the incoming data signal clock, a wide operating bandwidth, or wide-loop mode, is generally used.
In essence, the most difficult task to be performed in the receiving end of a data transmission system is not synchronizing the incoming data signal with the local clock, but rather the optimization of the transition between the necessary wide-loop mode and the more preferred narrow-loop mode. The operating bandwidth range of a clock recovery system using a PLL circuit is limited at the lower end by transmission clock frequency tolerances and at the upper end by desired receiver locking times.
In today's clock recovery schemes, the transition between PLL bandwidth modes is generally accomplished through the use of data signal edge statistics. Using the edge statistics for a typical type data transmission (i.e., voice data), a predetermined algorithm is invoked in the receiver hardware that forces the bandwidth of the PLL from wide-loop to narrow-loop mode. This type of statistics-based algorithm, which describes the phase variation of the incoming data edges with respect to the receiver clock edges, is generally acceptable where the environment is relatively noise-free. On the other hand, where the data transmission takes place in a noisy environment, the use of the narrow-loop mode becomes even more critical. Therefore, in order for incoming data to be received and decoded in as timely a manner possible, this transition must be optimized to meet all of the aforementioned criterion.
Accordingly, there exists a dire need for a data clock recovery scheme which addresses the need to optimize the transition between the required wide-loop bandwidth mode and the more desired narrow-loop bandwidth mode. Furthermore, the clock recovery scheme must address the additional requirements present in a noisy, or multi-path environment.